ASML (United States)

As EUV approaches high volume manufacturing, reticle defectivity becomes an even more relevant topic for further investigation. Current baseline strategy for EUV defectivity management is to design, build and maintain a clean system without pellicle. In order to secure reticle front side particle adders to an acceptable level for high volume manufacturing, EUV pellicle is being actively investigated. Last year ASML reported on our initial EUV pellicle feasibility. In this paper, we will update on our progress since then. We will also provide an update to pellicle requirements published last year. Further, we present experimental results showing the viability and challenges of potential EUV pellicle materials, including, material properties, imaging capability, scalability and manufacturability.

In this paper, a method for improving the process window is described by simultaneous source mask optimization (SMO). The method optimizes the source and mask of a critical pattern by optimizing the mask in the frequency domain. The minimum image log slope (ILS) is maximized at fragmentation points in the critical pattern while simultaneously maintaining the printing fidelity. The mask optimized in the frequency domain is then converted into a chromeless phase lithography (CPL) mask. The process window with the optimized source and optimized CPL mask doubles the aerial image contrast in comparison to an attenuating PSM with source optimization only. After optimizing the mask and source for a critical pattern, the remaining parts of the full-chip design are optimized with interference mapping. Another technique for optimizing the source for a full chip is presented in which the source is optimized by using the pitch frequency of the design. From the pitch frequency, the source is optimized by solving an integral equation for the first eigenfunction in which the first eigenfunction is calculated from the sum of coherent system (SOCS) representation of the transfer cross coefficient (TCC).

A spectroscopic, diffraction based technique is proposed in this paper as an alternative solution for overlay metrology in technology nodes below 90 nanometers. This novel technique extracts alignment error from broadband diffraction efficiency of specially designed diffraction targets in real-time. Feasibility of the technique is studied for a front-end process flow by measuring grating targets printed on a series of wafers which were intentionally mis-processed to introduce inter-die (grid) level programmed overlay errors. Correlation to conventional imaging overlay measurements is demonstrated. Short term and long term data sets demonstrate sub-half-nanometer in 3-sigma statistical parameters that characterize the diffraction overlay system, repeatability, reproducibility, Tool-Induced-Shift and tool-to-tool matching. The resulting total measurement uncertainty for this technique is thus demonstrated to be in the sub-nanometer range.

In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1). This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm², providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results. Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

Liquid immersion has been used for more than 100 years to increase the numeric aperture (NA) and resolution in optical microscopy. We explore the benefits and limitations of immersion technology in lithography. Immersion optical lithography has the potential to extend the resolution below 40 nm. The theory of immersion is decribed. Simulations show that a 193-nm immersion system at NA = 0.95 can double the depth of focus as compared to a dry system. Also, an immersion 193-nm system at NA = 1.05 has slightly more depth of focus than a 157-nm dry system at NA = 0.85. However, the exposure latitude at 193 nm is decreased due to the impact of polarization in imaging. Design schemes are presented to realize an immersion step and scan system. Two configuration approaches are proposed and explored. A localized shower type solution may be preferred over a bath type solution, because the impact on the step and scan platform design is significantly less. However, scanning over the wafer edge becomes the main design challenge with a shower solution. Studies are presented that look at the interaction of immersion fluids with the lens and the photoresist. Water seems to be a likely candidate, as it does not impact productivity of the step and scan system; however, focus and aberration levels need to be carefully controlled. For 157 nm, per-fluor-polyether (PFPE) materials are currently being studied, but their characteristics may limit the productivity of the exposure system. Further research on fluid candidates for 157-nm immersion is required.

Optical proximity effect is a well-known phenomenon in photolithography. Such an effect results from the structural interaction between the main feature and the neighboring features. Recent observations have shown that such structural interactions not only affect the critical dimension of the main feature at the image plane, but also the exposure latitude of the main feature. In this paper, it has been shown that the variation of the critical dimension as well as the exposure latitude of the main feature is a direct consequence of light field interference between the main feature and the neighboring features. Depending on the phase of the field produced by the neighboring features, the main feature exposure latitude can be improved by constructive light field interference, or degraded by destructive light field interference. The phase of the field produced by the neighboring features can be shown to be dependent on the pitch as well as the illumination angle. For a given illumination, the forbidden pitch lies in the location where the field produced by the neighboring features interferes with the field of the main feature destructively. The theoretical analysis given here offers the tool to map out the forbidden pitch locations for any feature size and illumination conditions. More importantly, it provides the theoretical ground for illumination design in order to suppress the forbidden pitch phenomenon, and for scattering bar placement to achieve optimal performance as well.

Towards the end of 2014, ASML committed to provide a EUV pellicle solution to the industry. Last year, during SPIE Microlithography 2015, we introduced the NXE pellicle concept, a removable pellicle solution that is compatible with current and future patterned mask inspection methods. This paper shows results of how we took this concept to a complete EUV pellicle solution for the industry. We will highlight some technical design challenges we faced developing the NXE pellicle and how we solved them. We will also present imaging results of pellicle exposures on a 0.33 NA NXE scanner system. In conjunction with the NXE pellicle, we will also present the supporting tooling we have developed to enable pellicle use.

As the semiconductor industry looks to the future to extend manufacturing beyond 100nm, ASML have developed a new implementation of an old optical method for lithography. Immersion lithography can support the aggressive industry roadmap and offers the ability to manufacture semiconductor devices at a low k1. In order to make immersion lithography a production worthy technology a number of challenges have to be overcome. This paper provides the results of our feasibility study on immersion lithography. We show through experimental and theoretical evaluation that we can overcome the critical concerns related to immersion lithography. We show results from liquid containment tests focussing on its effects on the scan speed of the system and the formation of micro-bubbles in the fluid. We present fluid-to-resist compatibility tests on resolution, using a custom-built interference setup. Ultimate resolution is tested using a home build 2 beam interference setup. ASML built a prototype full field scanning exposure system based on the dual stage TWINSCAN platform. It features a full field 0.75 NA refractive projection lens. We present experimental data on imaging and overlay.

Experiments and simulations were done to determine which pitches are forbidden for 130nm and 110nm features. Off axis illumination, annular and Quasar, and different reticle types, binary mask (BIM), 6 percent attenuating phase shift mask (PSM), 18 percent attenuating PSM, and alternating PSM were simulated and were exposed on an ASML PAS5500/700. Except for the 1:1 line to space ratio, Quasar for the BIM and the attenuated PSM had the largest process window without forbidden pitches. By increasing the transmission the exposure latitude increases. Increasing transmission, however, does not improve the depth of focus (DOF). Annular illumination was ineffective in increasing the DOF beyond 0.5micrometers for both the 130nm and 110nm features. The alternating PSM with low sigma had no forbidden pitches and had the largest DOF. Alternating PSM with high sigma however, was unable to resolve the dense pitches with sufficient process window.

Single exposure lithography is the most cost effective means of achieving critical level exposures, and extreme ultraviolet lithography (EUVL) is the technology that will enable this for 27nm production and below. ASML is actively engaged in the development of a multi generation production EUVL system platform that builds on TWINSCAN^TM technology and the designs and experience gained from the build, maintenance, and use of the Alpha Demo Tools (ADTs). The ADTs are full field step-and-scan exposure systems for EUVL and are being used at two research centers for EUVL process development by more than 10 of the major semiconductor chip makers, along with all major suppliers of masks and resist. In this paper, we will present our EUVL roadmap, and the manufacturing status of the projection lens for our first production system. Included will also be some test data on the new reticle pods. Experimental results from ADT showing the progress in imaging (28 nm half pitch 1:1 lines/spaces CDU ~10%), single machine overlay down to 3 nm, and resist complete the paper.

We have investigated a number of key resist factors using EUV lithography including activation energy of deprotection. Our standard high activation resist material, MET-2D (XP5271F), is capable of robust performance at CDs in 40 nm regime and thicknesses above 100 nm. Below 100 nm film thickness, controlling acid diffusion becomes a difficult challenge. We have also developed a low activation resist (XP6305A) which shows superior process window and exposure latitude at CDs in the 35 nm regime. This resist is optimal for 80 nm film thickness. Lastly, we have demonstrated 25 nm 1:1 resolution capability using a novel chemical amplification resist called XP6627. This is the first EUV resist capable of 25 nm resolution. The LER is also very low, 2.7 nm 3&sgr;, for the 25 nm features. Our first version, XP6627G, has a photospeed of 40 mJ/cm². Our second version, XP6627Q, has a photospeed of 27 mJ/cm². Our current focus is on improving the photospeed to less than 20 mJ/cm². The outstanding resolution and LER of this new resist system raises the possibility of extending chemically amplified resist to the 22 nm node.

This paper presents a comprehensive study of the impact of wavefront errors on low-k1-imaging performance using high numerical aperture NA lithographic systems. In particular, we introduce a linear model that correctly describes the aberration induced imaging effects. This model allows us to quantify the aberration requirements for future lithographic nodes. Moreover, we derive scaling laws characterizing the imaging performance in dependence on the key parameters exposure wavelength &#955;, NA, and k1. Our investigations demonstrate, first, that an accurate control of coma is and will be crucial, and, second, that spherical requirements will be very tight for k1<0.3 due to isolated contact printing. Finally, we summarize the results of this paper in a roadmap covering the aberration requirements in optical lithography down to the 45nm node. We conclude that the improvement of wavefront quality is necessary to enable imaging enhancement techniques, but is not sufficient to replace these techniques.

Current roadmaps show that the semiconductor industry continues to drive the usable Rayleigh resolution towards the fundamental limit (for 50% duty cycle lines) at k₁=0.25. This is being accomplished through use of various resolution enhancement technologies (RETs), extremely low aberration optics with stable platforms, and resists processes that have ever-increasing dissolution contrast and smaller diffusion lengths. This talk will give an overview of the latest optical mechanisms that can be used to improve the imaging system for low k₁ resolutions. We show 3 non-photoresist techniques to measure the optical parameters of a scanner: 1) a new fast phase measurement interferometer to measure aberrations is presented with an accuracy and repeatability of <3m&lambda;, 2) we introduce a method to measure the illumination profile of the exposing source, and 3) a measurement system to monitor scattered light is presented with correlation to other techniques using a salted pellicle experiment to create controlled scattered light. The optimization of illumination and exposure dose is presented. We show the mechanism for customizing illumination based on specific mask layers. We show how this is done and compare process windows to other more conventional modes such as annular illumination or QUASAR. The optimum design is then implemented into hardware that can give extremely high optical efficiency. We also show how system level control mechanisms can be used to field-to-field and across-field exposure to compensate for lithography errors. Examples of these errors can include reticle CD deviations, wavefront aberrations, and across-field illumination uniformity errors. CD maps, facilitated by SEM and ELM, can give the prescribed changes necessary. We present a system that interfaces to new hardware to compensate these effects by active scanner corrections.

The Engineering Test Stand (ETS) is an EUV lithography tool designed to demonstrate full-field EUV imaging and provide data required to accelerate production-tool development. Early lithographic results and progress on continuing functional upgrades are presented and discussed. In the ETS a source of 13.4 nm radiation is provided by a laser plasma source in which a Nd:YAG laser beam is focused onto a xenon- cluster target. A condenser system, comprised of multilayer-coated and grazing incidence mirrors, collects the EUV radiation and directs it onto a reflecting reticle. The resulting EUV illumination at the reticle and pupil has been measured and meets requirements for acquisition of first images. Tool setup experiments have been completed using a developmental projection system with (lambda) /14 wavefront error (WFE), while the assembly and alignment of the final projection system with (lambda) /24 WFE progresses in parallel. These experiments included identification of best focus at the central field point and characterization of imaging performance in static imaging mode. A small amount of astigmatism was observed and corrected in situ, as is routinely done in advanced optical lithographic tools. Pitch and roll corrections were made to achieve focus throughout the arc-shaped field of view. Scan parameters were identified by printing dense features with varying amounts of magnification and skew correction. Through-focus scanned imaging results, showing 100 nm isolated and dense features, will be presented. Phase 2 implementation goals for the ETS will also be discussed.

With the realization of the &alpha;-tool, ASML is progressing with the pre-commercialization phase of its EUVL development. We report on the progress in the development of several key modules of the &alpha;-tool, including the source, wafer stage and reticle stage, wafer handling, baseframe, and optics modules. We demonstrate that the focus sensor meets its vacuum requirements, and that both stages after limited servo optimization approach the required scanning performance. A particle detection system has been built for the qualification of the reticle handling module, and preliminary results show that 50nm particles can be detected. The optics lifetime program showed substantial progress by utilizing caplayers to MoSi samples in order to suppress oxidation caused by H₂O molecules under EUV illumination: a suppression &ge; 100x is achieved, compared to uncapped MoSi.

EUV lithography for resolution below 8 nm half pitch requires the numerical aperture (NA) of the projection lens to be significantly larger than the current state-of-the-art 0.33NA. In order to be economically viable, a throughput in the range of 100 wafers per hour is needed. As a result of the increased NA, the incidence angles of the light rays at the mask increase significantly. Consequently the shadowing and the variation of the multi-layer reflectivity deteriorate the aerial image contrast to unacceptably low values at the current 4x magnification. The only solution to reduce the angular range at the mask is to increase the magnification. Simulations show that we have to double the magnification to 8x in order to overcome the shadowing effects. Assuming that the mask infrastructure will not change the mask form factor, this would inevitably lead to a field size that is a quarter of the field size of current 0.33NA step and scan systems. This would reduce the throughput of the high-NA scanner to a value significantly below 100 wafers per hour unless additional measures are taken. This paper presents an anamorphic step and scan system capable to print fields that are half the field size of the current full field. The anamorphic system has the potential to achieve a throughput in excess of 150 wafers per hour by increasing the transmission of the optics as well as increasing the acceleration of the wafer stage and mask stage. This makes it an economically viable lithography solution. The proposed 4x/8x magnification is not the only logical solution. There are potentially other magnifications to increase the scanner performance while at the same time reducing the mask requirements.

The ASML extreme ultraviolet lithography (EUV) alpha demo tool is a 0.25NA fully functional lithography tool with a field size of 26&times;33 mm², enabling process development for sub-40-nm technology. Two exposure tools are installed at customer facilities, and are equipped with a Sn discharge source. In this paper we present data measured at intermediate focus of the Sn source-collector module. We also present performance data from both exposure tools, show the latest results of resist exposures including excellent 32-nm half pitch dense staggered and aligned contact hole images, and present the highlights of the first demonstration of an electrically functional full field device with one of the layers made using EUVL in ASML's alpha demo tool.

The wafer alignment system plays a key role in the reduction of product overlay. This reduction allows shrink of current products and tighter overlay design rules on next generation products. Further reduction of product overlay numbers requires continuous research in the field of interaction between wafer mark and alignment sensor. We explain how this research and various IC manufacturing requirements drive wafer alignment system design and how these requirements are met in two new phase-grating based wafer alignment concepts. This paper describes and compares these two new concepts that extend ASML's current ATHENATM alignment system. The first concept we describe is an extension of ATHENATM which uses a smaller alignment illumination beam. The second concept adds a self-referencing interferometer, combined with a high numerical aperture objective. Each concept targets a specific range of performance parameters, such as greater mark layout flexibility and the possibility to use more than two illumination wavelengths. We will show how both concepts clearly add to the existing ATHENATM sensor performance; focus-tilt sensitivity reduces with a factor of 5 to 20 for concept A and B respectively. Both concepts will be further developed.

Various factors, such as lens aberrations, system vibration and the choice of illumination polarization can degrade the level of modulation, and hence, image quality. This paper discuses the sensitivity of multiple feature types to these factors. It is shown that aberration sensitivity increases linearly with decreasing resolution, scaled to the Rayleigh criteria. An analysis of the vibration tolerance is done for transverse and axial vibration planes, where the effects on the process window and CD uniformity are measured. The vibration is shown to decrease the process window greater for low contrast images and is shown to scale directly with the resolution. The new millennium will usher in optical system with very high NA lenses for 248nm, 193nm and 157nm. This paper re-examines the role of the polarization on required specifications of the exposure tool optics. It is found that tight polarization specifications with &lt; 10 residual polarization will be needed for future systems.

We present a complete method for the characterization and modeling of flare based on the measurement of the modulation transfer function (MTF) of scanners. A point-spread function (PSF<SUB>scat</SUB>) representing only the scattered light or flare in the tool is inferred by comparing the measured MTF with a calculated MTF for aberration-free imaging. This PSF<SUB>scat</SUB> is then used to predict the effect of flare for different layouts. In particular, local variations in pattern density are shown to couple with mid- and short-range flare and lead to significant CD non-uniformity across the field. Finally, we examine double exposure techniques that are sensitive to flare because of the total light reaching the wafer, from the two masking steps.