Institut de Microélectronique, Electromagnétisme et Photonique

Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and <emphasis emphasistype="smcaps">on</emphasis>– <emphasis emphasistype="smcaps">off</emphasis> current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased. </para>

An air-filled substrate integrated waveguide (SIW) made of a multilayer printed circuit board process is proposed in this paper. It is of particular interest for millimeter-wave applications that generally require low cost and low-loss performance and excellent power-handling capability. This three-layered air-filled SIW allows for substantial loss reduction and power-handling capability enhancement. The top and bottom layers may make use of a low-cost standard substrate such as FR-4 on which baseband or digital circuits can be implemented so to obtain a very compact, high-performance, low-cost, and self-packaged millimeter-wave integrated system. Over Ka-band (U-band), it is shown that the air-filled SIW compared to its dielectric-filled counterparts based on Rogers substrates RT/Duroid 5880 and also 6002 reduces losses by a mean value of 0.068 dB/cm (0.098 dB/cm) and 0.104 dB/cm (0.152 dB/cm), increases average power-handling capability by 8 dB (6 dB) and 7.5 dB (5.7 dB), and quality factor by 2.7 (2.8) and 3.6 (3.8) times, respectively. The peak power-handling capability of the proposed structure is also studied. A wideband transition is presented to facilitate interconnects of the proposed air-filled SIW with dielectric-filled SIW. Design steps of this transition are detailed and its bandwidth limitation due to fabrication tolerances is theoretically examined and established. For validation purposes, a back-to-back transition operating over the Ka-band is fabricated. It achieves a return loss of better than 15 dB and an insertion loss of 0.6 ±0.2 dB ( 0.3 ±0.1 dB for the transition) from 27 to 40 GHz. Finally, two elementary circuits, namely, the T-junction and 90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> hybrid coupler based on the air-filled SIW, are also demonstrated.

The operation of 1-3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mode (for either front or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, a large influence of substrate depletion underneath the buried oxide, the absence of drain current transients, and degradation in electron mobility are typical effects in these ultra-thin MOSFETs. The comparison of SG and DG configurations demonstrates the superiority of DG-MOSFETs: ideal subthreshold swing and remarkably improved transconductance (consistently higher than twice the value in SG-MOSFETs). The experimental data and the difference between SG and DG modes is explained by combining classical models with quantum calculations. The key effect in ultimately thin DG-MOSFETs is volume inversion, which primarily leads to an improvement in mobility, whereas the total inversion charge is only marginally modified.

Organic field-effect transistors (OFETs) suffer from limitations such as low mobility of charge carriers and high access resistance. Direct and accurate evaluation of these quantities becomes crucial for understanding the OFETs properties. We introduce the Y function method (YFM) to pentacene OFETs. This method allows us to evaluate the low-field mobility without the access or contact resistance influence. The low-field mobility is shown to be more appropriate than the currently applied field-effect mobility for the OFETs’ performance evaluation. Its unique advantage is to directly suppress the contact resistance influence in individual transistors, although such contact resistance is a constant as compared to the widely accepted variable one with respect to the gate voltage. After a comparison in detail with the transmission-line method, the YFM proved to be a fast and precise alternative method for the contact resistance evaluation. At the same time, how the contact resistance affects the effective mobility and the field-effect mobility in organic transistors is also addressed.

In this paper, the use of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in a convolutional neural network (CNN) is studied. We employed an artificial synapse composed of multiple OxRAM cells connected in parallel, thereby providing synaptic efficacies. Electrical characterization results show that the proposed HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based OxRAM technology offers good electrical properties in terms of endurance (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> cycles), speed (<;10 ns), and low energy (<;10 pJ), and thus being well suited for neuromorphic applications. A device physical model is developed in order to study the variability of the resistance as a function of the stochastic position of oxygen vacancies in 3-D. Finally, the proposed binary OxRAM synapse has been used for CNN system-level simulations. High accuracy (recognition rate > 98%) is demonstrated for a complex visual pattern recognition application. We demonstrated that the resistance variability and the reduced memory window of the OxRAM cells when operated at extremely low programming conditions (<;10 pJ per switching event) have a small impact on the performances of proposed OxRAM-based CNN (recognition rate 94%).

Ultrathin piezoelectric nanogenerator (NG) with a total thickness of ≈16 μm is fabricated as an active or self‐powered sensor for monitoring local deformation on a human skin. The NG was based on an anodic aluminum oxide (AAO) as an insulating layer grown on a thin Al foil by anodization, on which a thin film made of aligned ZnO nanowire compacted arrays is grown by solution chemistry. The performance of the NG is characterized with the assistance of the finite element method (FEM) simulation. The extremely thin NG is attached on the surface of an eyelid, and its output voltage/current characterizes the motion of the eye ball underneath. Since there is no external power needed for the operation of the NG, this self‐powered or active sensor can be effective in monitoring sleeping behavior, brain activities, and spirit status of a person as well as any biological associated skin deformation.

The CRC Concise Encyclopedia of Nanotechnology sets the standard against which all other references of this nature are measured. As such, it is a major resource for both skilled professionals and novices to nanotechnology.The book examines the design, application, and utilization of devices, techniques, and technologies critical to research at the

Diagnosing of the interface quality and the interactions between insulators and semiconductors is significant to achieve the high performance of nanodevices. Herein, low-frequency noise (LFN) in mechanically exfoliated multilayer molybdenum disulfide (MoS2) (~11.3 nm-thick) field-effect transistors with back-gate control was characterized with and without an Al2O3 high-k passivation layer. The carrier number fluctuation (CNF) model associated with trapping/detrapping the charge carriers at the interface nicely described the noise behavior in the strong accumulation regime both with and without the Al2O3 passivation layer. The interface trap density at the MoS2-SiO2 interface was extracted from the LFN analysis, and estimated to be Nit ~ 10(10) eV(-1) cm(-2) without and with the passivation layer. This suggested that the accumulation channel induced by the back-gate was not significantly influenced by the passivation layer. The Hooge mobility fluctuation (HMF) model implying the bulk conduction was found to describe the drain current fluctuations in the subthreshold regime, which is rarely observed in other nanodevices, attributed to those extremely thin channel sizes. In the case of the thick-MoS2 (~40 nm-thick) without the passivation, the HMF model was clearly observed all over the operation regime, ensuring the existence of the bulk conduction in multilayer MoS2. With the Al2O3 passivation layer, the change in the noise behavior was explained from the point of formation of the additional top channel in the MoS2 because of the fixed charges in the Al2O3. The interface trap density from the additional CNF model was Nit = 1.8 × 10(12) eV(-1) cm(-2) at the MoS2-Al2O3 interface.

The integrated nanogenerator (NG) based on vertical nanowire (NW) arrays is one of the dominant designs developed to harvest mechanical energy using piezoelectric nanostructures. Finite element method (FEM) simulations of such a NG are developed using ZnO NWs in compression mode to evaluate its performances in term of piezoelectric potential generated, capacitance, induced mechanical energy, output electrical energy, and efficiency. This evaluation is essential to correctly understand NG operation. Three main issues are highlighted. The mechanical and electrical structures of the NG as an integrated system are optimized, and strategies for concentrating the mechanical strain field in the NWs and increasing the force sensitivity are developed. In addition, the influence of NWs length and diameter on NG performances is investigated. The optimization results in a piezoelectric nano composite material where global performances are improved by mean of long and thin NWs.

The feasibility of split capacitance-voltage (C-V) measurements in sub-0.1 μm Si MOSFETs is demonstrated. Based on the split C-V measurements, an improved methodology to extract accurately the effective channel length and the effective mobility is proposed. Unlike conventional I/sub d/(V/sub g/)-based extraction techniques, this new approach does not assume the invariance of the effective mobility with gate length (assumption proved to be false in this paper). This method is relevant to study transport limitations in ultimate MOSFETs as illustrated with the study of pocket implant influence on 50-nm p-MOSFETs.

The generation and propagation of single event transients (SET) is measured and modeled in SOI inverter chains with different designs. SET propagation in inverter chains induces significant modifications of the transient width. In some cases, a "propagation-induced pulse broadening" (PIPB) effect is observed. Initially narrow transients, less than 200 ps at the struck node, are progressively broadened up to the nanosecond range, with the degree of broadening dependent on the transistor design and the length of propagation. The chain design (transistor size and load) is shown to have a major impact on the transient width modification.

The reduction of the supply voltage is standard MOSFETs is impeded by the subthreshold slope, which cannot be lowered below 60 mV/decade, even in ideal fully-depleted devices. We review selected CMOS-compatible devices capable of switching more abruptly than MOSFETs, and discuss their merits and limitations. Tunneling FETs (TFETs) are reverse-biased gated PIN diodes where the gate controls the electric field in the interband tunneling junction. Technological solutions for improved performance will be described, including alternative channel materials and geometries, as well as a proposed paradigm shift of increasing the current drive by internal amplification in the bipolar-enhanced TFET. Other emerging sharp-switching mechanisms are reviewed, including the abrupt change in the polarization of ferroelectric materials, mechanical contact in nano-electro-mechanical systems, energy filtering of injected carriers, etc. Recently proposed band modulation feedback transistors are conceptually different from MOSFETs or TFETs. They have similar gated-diode configuration, but are operated in forward-bias mode. Electrostatic barriers are formed (via gate biasing) to prevent electron/hole injection into the channel until the gate or drain bias reaches a turn-on value. Due to bandgap modulation along the channel, these devices can switch abruptly (<;1 mV/decade) to a high current.

This paper describes a new concept of substrate integrated waveguide (SIW): a slow-wave substrate integrated waveguide (SW-SIW). Compared to a conventional SIW, the proposed topology requires a double-layer substrate with a bottom layer including internal metallized via-holes connected to the bottom conductive plane. The slow-wave effect is obtained by the physical separation of electric and magnetic fields in the structure. Electromagnetic simulations show that this topology of SIW allows decreasing the longitudinal dimension by more than 40% since the phase velocity is significantly smaller than that of a classical SIW. Simultaneously, the lateral dimension of the waveguide is also reduced. By considering a double-layer technology, SW-SIWs exhibiting a cutoff frequency of 9.3 GHz were designed, fabricated, and measured. The transversal dimension and the phase velocity of the proposed SW-SIW are both reduced by 40% as compared to a classical SIW designed for the same cutoff frequency, leading to a significant surface reduction. Moreover, an original kind of taper is proposed to achieve a good return loss when the SW-SIW is fed by a microstrip transmission line.

The growth of ZnO nanowires by chemical bath deposition (CBD) is of great potential for their integration into nanoscale devices. However, the effects of the chemical precursors in solution are still under debate, such as the role of hexamethylenetetramine (HMTA). In order to tackle this issue, these effects are thoroughly disentangled from the effects of the structural morphology of the ZnO seed layer and investigated through a large number of nonequimolar CBDs over a broad range of chemical precursor concentrations and ratios. The analysis is further supported by thermodynamic simulations yielding theoretical solubility plots and speciation diagrams of Zn(II) species. It is shown that the ZnO deposited volume and, to some extent, the length of ZnO nanowires are directly related to the supersaturation in solution, which strongly depends on the chemical precursor concentration and pH. A slight excess of HMTA with respect to zinc nitrate is required to reach the largest axial growth rate of ZnO nanowires. In addition to act as a source of HO– ions, HMTA is found to act as a pH buffer over a broad range of chemical precursor concentrations and ratios, except for its largest excess. Additionally, it is unambiguously revealed that HMTA strongly reduces the radial growth of ZnO nanowires, by inhibiting the development of their nonpolar m-plane sidewalls. Importantly, HMTA also affects significantly the density of ZnO nanowires and hence their nucleation process, which is attributed to its significant interaction with the ZnO seed layer. The present findings give a deeper insight into the multiple roles of HMTA, which are an important step toward the ultimate control of the structural uniformity of ZnO nanowire arrays.

An expression is derived for the maximum proportion of remaining samples in the sample selection technique for mode-stirred chamber measurements. The limit is independent of the selection algorithm used. The limit is verified in simulations as well as measurement examples.

We have studied the magnetic properties of ${\mathrm{Na}}_{2}{\mathrm{Co}}_{2}{\mathrm{TeO}}_{6}$, which features a honeycomb lattice of magnetic ${\mathrm{Co}}^{2+}$ ions, through macroscopic characterization and neutron diffraction on a powder sample. We have shown that this material orders in a zigzag antiferromagnetic structure. In addition to allowing a linear magnetoelectric coupling, this magnetic arrangement displays very peculiar spatial magnetic correlations, larger in the honeycomb planes than between the planes, which do not evolve with the temperature. We have investigated this behavior by classical Monte Carlo calculations using the ${J}_{1}\text{\ensuremath{-}}{J}_{2}\text{\ensuremath{-}}{J}_{3}$ model on a honeycomb lattice with a small interplane interaction. Our model reproduces the experimental neutron structure factor, although its absence of temperature evolution must be due to additional ingredients, such as chemical disorder or quantum fluctuations enhanced by the proximity to a phase boundary.

A high-quality smart filter for terahertz range with relative tunability reaching 20% has been demonstrated. The filter is based on a narrow transmission band, which originates from a defect mode that appears due to insertion of a single crystal of KTaO3 into otherwise periodic one-dimensional photonic crystal. Frequencies of defect modes are controlled by the refractive index of the defect: their high tunability is achieved by the strong temperature dependence of the dielectric properties of KTaO3. The low losses of KTaO3 lead to a high peak transmission of the filter. Influence of the defect losses on the properties of the filter is also discussed.

This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices.