A regular parallel RSA processor
Published • Dec 23, 2004
Authors:,,
Qiang Liu
Fangzhen Ma
Dong Tong
Abstract
High performance VLSI implementation of the RSA algorithm using the systolic array is presented. High-speed applications of RSA systems require parallel implementations of modular multipliers. Besides using the systolic architecture which is popular in hardware-based RSA systems, a block-based schem...
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