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Timing‐Driven Circuit Implementation

Published in VLSI design • Jan 1, 1998
NobleIDNI1P48W87R15S10
Authors:
Dimitrios Karayiannis
,
Spyros Tragoudas

Abstract

We consider the problem of selecting the proper implementation of each circuit module from a cell library to minimize the propagation delay along every path from any primary input to any primary output subject to an upper bound on the total area of the circuit. Different module implementations may h...

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