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A performance-driven layer assignment algorithm for multiple interconnect trees

Published • Jan 1, 1998
NobleIDNI7P05W30R21S13
Authors:
Prashant Saxena
,
C. L. Liu

Abstract

With the advent of DSM technologies, interconnect delays increasingly overshadow the transistor delays. Furthermore, since the electrical characteristics of different layers in multilayer routing technologies vary widely, the assignment of the interconnect tree edges to specific routing layers has a...

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