Python based high-level synthesis compiler
Published in Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE • Nov 25, 2014
NobleIDNI5P44W10R66S08
Authors:,,
Radosław Cieszewski
K. Późniak
Ryszard S. Romaniuk
Abstract
This paper presents a python based High-Level synthesis (HLS) compiler. The compiler interprets an algorithmic description of a desired behavior written in Python and map it to VHDL. FPGA combines many benefits of both software and ASIC implementations. Like software, the mapped circuit is flexible,...
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