Cache persistence analysis
Published in ACM Transactions on Embedded Computing Systems • Mar 1, 2013
NobleIDNI9P37W92R24S80
Authors:
Christoph Cullmann
Abstract
To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of the cache analysis is the categorization of the ...
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