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Parallel decoding cyclic burst error correcting codes

Published • Jan 1, 2003
NobleIDNI5P76W66R54S55
Authors:
Ganesan Umanesan
,
Eiji Fujiwara

Abstract

Burst error correcting codes have traditionally been decoded using linear feedback shift registers (LFSR). However, these sequential decoding schemes are not suitable for applications where a high speed parallel decoding employing only combinational logic circuitry is required. This paper presents a...

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