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Precise shared cache analysis using optimal interference placement

Published • Apr 1, 2014
NobleIDNI3P74W51R64S12
Authors:
Kartik Nagar
,
Y. N. Srikant

Abstract

Determining the Worst Case Execution Time (WCET) of programs running on a multi-core architecture is a challenging problem, that is hampering the use of multi-cores in real-time systems. The highly imprecise WCET estimates obtained using the current state-of-the-art analyses has prompted research in...

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