Monolithic SMPTE Time Code Reader LSI using Gate Array
Published in IEEE Transactions on Broadcasting • Dec 1, 1983
NobleIDNI0P90W02R73S65
Authors:,,
Kiichi Kobayashi
Masashi Nakamura
Hideki Kokubun
Abstract
This paper describes an SMPTE time code reader LSI using gate arrays. The reader consists of two chips, i.e., a bit clock extracting chip, and a display interface chip. All circuits are designed with random logic gates.
Finding related papers...
Discussions
(0)No comments yet
Be the first to share your thoughts!