A FASTBUS Processor Interface Using a 68000 Microprocessor
Published in IEEE Transactions on Nuclear Science • Jan 1, 1984
NobleIDNI2P67W86R52S90
Authors:,,
Y. Arai
T. Murakami
Eiji Inoue
Abstract
A versatile FASTBUS master utilize a 68000 microprocessor has been developed. The module implements geographical, logical and broadcast addressing and is able to handle the FASTBUS Service Request. The data transfer rate is about 800 kB/sec by using window driver. The logics and test results are des...
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