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Evaluating alternative implementations for LDPC decoder check node function

Published in IEEE Computer Society Annual Symposium on VLSI • Oct 4, 2004
NobleIDNI1P05W05R06S15
Authors:
Theocharis Theocharides
,
Greg Link
,
Eric J. Swankoski

Abstract

Low density parity checks (LDPC) are a method of error detection and correction that are able to achieve near Shannon-limit channel communication. LDPC decoders involve a series of computations between two units, the check node and the bit node. In this paper we propose the use of an approximation u...

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