The authors present a placement algorithm that uses the notion of partial scan and that addresses testability as well as performance. The cost of including a flip-flop cell in a scan path is obtained in the placement process and guides the selection of scan flip-flops. This is then followed by a cell resizing step in which logic cells change their widths and timing characteristics using the templates provided by a cell library. This reduces delays in the critical timing paths and delays caused by inserting scan flip-flops. Experimental results on the ISCAS benchmark show that combining the performance and testability optimizations in the placement level resulted in better solutions in terms of area, timing, and fault coverage. >