A cache-based method for accelerating switch-level simulation
Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • Jan 1, 1994
Authors:,
Larry G. Jones
David Blaauw
Abstract
Switch-level simulation has become a common means of validating the behavior of MOS circuits. In this paper, we present a new cache-based simulation method that significantly reduces the cost of subnetwork evaluation during switch-level simulation. The method speeds up simulation by as much as a fac...
Finding related papers...
Discussions
(0)No comments yet
Be the first to share your thoughts!