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PROGRAMMING FOR PARALLEL PATTERN GENERATORS

Published • Aug 24, 2005
NobleIDNI6P45W39R87S82
Authors:
M. Kanzaki
,
Masahiro Ishida

Abstract

This paper a!escribes the design and use of parallel pattern generaliors in a Memory Test System to achieve high speed testing of memory integrated circuitdr. Both the hardware design and the software design of this subsystem is described. This Test System has been put into practical use and has res...

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