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A path selection algorithm for timing analysis

Published in Design Automation Conference • Jun 1, 1988
NobleIDNI7P07W47R38S57
Authors:
Hsu‐Chun Yen
,
S. Ghanta
,
Hang Du

Abstract

Due to the rapid progress in semiconductor technology, the number of gates that can be placed in a chip increases dramatically. Existing algorithms for timing analysis have difficulties when dealing with large designs. A new algorithm for timing analysis is proposed in this paper. This algorithm enu...

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