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Algorithm-based low-power transform coding architectures

Published • Jan 1, 1995
NobleIDNI9P24W32R27S81
Authors:
An-Yeu Wu
,
K. J. Ray Liu

Abstract

In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes down. In this paper, we propose new algorithmic-level techniques for compensating the increased delays based on the multir...

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