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Single chip array processor for high performance design error simulation

Published • Nov 19, 2002
NobleIDNI9P11W14R90S07
Authors:
Sungho Kang
,
Stephen A. Szygenda

Abstract

This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation c...

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