Error Detection Using Dynamic Dataflow Verification
Published in International Conference on Parallel Architectures and Compilation Techniques • Sep 15, 2007
NobleIDNI8P31W06R82S09
Authors:,
Albert Meixner
Daniel J. Sorin
Abstract
A significant fraction of the circuitry in a modern processor is dedicated to converting the linear instruction stream into a representation that allows the execution of instructions in data dependence order, rather than program order, to extract instruction level parallelism. All errors caused by h...
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