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Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

Published in International Symposium on Microarchitecture • Dec 1, 2007
NobleIDNI3P08W14R86S08
Authors:
Jangwoo Kim
,
Nikos Hardavellas
,
Ken Mai

Abstract

In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses, soft and hard errors in the memory system will increase and single error events are more likely to cause large-scale m...

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