Test pattern generation using Boolean satisfiability
Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • Jan 1, 1992
Authors:
T. Larrabee
Abstract
The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: first, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits,...
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