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HAL III: function level hardware logic simulation

Published • Dec 4, 2002
Authors:
Shigeru Takasaki
,
Nobuyoshi Nomizu
,
Yoshihiro Hirabayashi

Abstract

A function-level hardware simulator, HAL III, is described. HAL III can simulate a circuit model written by a register transfer level language FDL without translating it into gate level. It adopts parallel, pipeline, and flexible FDL evaluation architectures, and uses level sort and event-driven alg...

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