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A high speed parallel structure for the basic wavelet transform algorithm

Published in 1993 IEEE International Symposium on Circuits and Systems • Aug 24, 2005
NobleIDNI7P60W80R12S24
Authors:
H. Khali
,
J.L. Houle
,
Yvon Savaria

Abstract

This paper gives a new architecture that can support wavelet analysis in both compression and dilation. Its efficiency allows processing at speeds of up to one input sample per clock cycle without buffering. Therefore, it can generate several wavelet coefficients at the same time. This architecm is ...

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