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Published in Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture • Oct 11, 2019
NobleIDNI2P48W40R48S67
Authors:
Xiao Liu
,
David Roberts
,
Rachata Ausavarungnirun

Abstract

As memory capacity scales, traditional cache and memory hierarchy designs are facing increasingly difficult challenges in ensuring high reliability with low storage and performance cost. Recent developments in 3D die-stacked DRAM caches and nonvolatile memories (NVRAMs) introduce promising opportuni...

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