Compressed Cache Layout Aware Prefetching
Published in Symposium on Computer Architecture and High Performance Computing • Oct 1, 2019
Authors:,,
Niloofar Charmchi
Caroline Collange
André Seznec
Abstract
The speed gap between CPU and memory is impairing performance. Cache compression and hardware prefetching are two techniques that could confront this bottleneck by decreasing last level cache misses. However, compression and prefetching have positive interactions, as prefetching benefits from higher...
Finding related papers...
Discussions
(0)No comments yet
Be the first to share your thoughts!