A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems
Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • Nov 25, 2020
Authors:,
Supriyo Maji
Cheng‐Kok Koh
Abstract
Timing violations in high performance communication channels in system-on-chips (SoC) may occur in the late stages of the physical design process. To address that, latency insensitive systems (LISs) employ pipelining in the communication channels through the insertion of relay stations. Although the...
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