A* is an informed pathfinding algorithm that depends on an accurate heuristic function to search for the shortest path. A complex pathfinding problem requires a well-informed heuristic function to efficiently process all data and compute the next move. Hence, designing good heuristic functions for specific domains becomes the primary research focus on pathfinding algorithms optimization. However, designing new heuristic functions is time consuming and difficult. Evolutionary Heuristic A* (EHA*) search proposed to have a self-evolving heuristic function to reduce the engineering efforts on heuristic functions design. The Genetic Algorithm is one of the most popular and efficient optimization techniques that is based on the Darwinian principle of survival of the fittest. It has been successfully applied on many complex real world applications including VLSI circuit partitioning, Travelling Salesman Problem (TSP), and robotic designs. Although the Genetic Algorithm is proved to be efficient on solving complex problems, the amount of computations and iterations required for this method is enormous. Therefore, we propose a hardware accelerator architecture for EHA* that is implemented on a Field Programmable Gate Array(FPGA) by employing a combination of pipelining and parallelization to achieve better performance. Moreover, the proposed Genetic Algorithm accelerator can be customized in terms of the population size, number of generations, crossover rates, and mutation rates for flexibility. The FPGA accelerator proposed in this paper achieves more than 8x speed up compared to the software implementation.