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Cache aware compression for processor debug support

Published • Apr 1, 2009
NobleIDNI3P49W59R19S71
Authors:
Anant Vishnoi
,
Preeti Ranjan Panda
,
S. Balakrishnan

Abstract

During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, the bulk of which is composed of cache, the problem is essentially that of transferring cache contents off-chip, to a logic a...

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