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Memory-efficient interconnect optimization

Published in Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) • Nov 13, 2002
NobleIDNI8P80W21R93S74
Authors:
Minghorng Lai
,
D.F. Wong

Abstract

Interconnect design has emerged as one of the major challenges facing chip designers as VLSI manufacturing progresses and gate sizes scale down. Dynamic programming (DP) is an efficient and robust technique for finding optimal solutions to interconnect optimization problems in VLSI design. However, ...

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