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COS/MOS parallel processor array

Published • Jan 1, 1970
NobleIDNI2P52W81R42S08
Authors:
A. Alaspa
,
A. Dingwall

Abstract

A report on an LSI, COS/MOS parallel processor array posessing functional capabilities of an arithmetic unit 4-bit slice, will be presented. High functional density was achieved using functional gating and transmission gating to reduce device requirements. The data-transfer rate for a 4-bit add is 1...

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