COS/MOS parallel processor array
Published • Jan 1, 1970
NobleIDNI2P52W81R42S08
Authors:,
A. Alaspa
A. Dingwall
Abstract
A report on an LSI, COS/MOS parallel processor array posessing functional capabilities of an arithmetic unit 4-bit slice, will be presented. High functional density was achieved using functional gating and transmission gating to reduce device requirements. The data-transfer rate for a 4-bit add is 1...
Finding related papers...
Discussions
(0)No comments yet
Be the first to share your thoughts!