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Systematic address and control code transformations for performance optimisation of a MPEG-4 video decoder
Palkovic, Miranda, Denolf and 2 others
Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design25 Jun 2003
NobleIDark:/48914/w1/20260515/4EF06344DOI10.1109/aspdac.2002.994978
Systematic address and control code transformations for performance optimisation of a MPEG-4 video decoder
Palkovic, Miranda, Denolf and 2 others · Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design · 2003 · Subscription
NobleIDark:/48914/w1/20260515/4EF06344DOI10.1109/aspdac.2002.994978
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Abstract
A cost-efficient realisation of an advanced multimedia system requires high-level memory optimisations to deal with the dominant memory cost. This typically results in more efficient code for both power and system bus load. However, significant performance improvement can also be achieved when carefully optimising the address functionality. This paper shows how the nature of this addressing code and the related control flow allows transformation of the complex index, iterator and condition expressions into efficient arithmetic. We apply our address optimisation (ADOPT) design technology to a low power memory optimised MPEG-4 decoder When mapped on popular programmable multimedia processor architectures, we obtain a factor of 2 in performance gain.