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Cache persistence analysis

Published in ACM SIGPLAN Notices • May 18, 2012
NobleIDNI0P19W71R43S94
Authors:
Christoph Cullmann

Abstract

To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of the cache analysis is the categorization of the ...

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