Processor coupling
Published in ACM SIGARCH Computer Architecture News • Apr 1, 1992
Authors:,
Stephem W. Keckler
William J. Dally
Abstract
The technology to implement a single-chip node composed of 4 high-performance floating-point ALUs will be available by 1995. This paper presents processor coupling, a mechanism for controlling multiple ALUs to exploit both instruction-level and inter-thread parallelism, by using compile time and run...
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