This chapter presents a high-level overview of automated technologies for taking an embedded program, parallelizing it, and mapping it to a parallel processor. As the hardware architecture community moves forward with processing capability, new programming models and tools are necessary to truly harness the power of these architectures. Software accounts for significantly more of the government spending than does hardware because as processor architectures change so must the software. Automatic code optimization is a rich area of research. An important concept to note is that a map abstracts away a large number of details about underlying processing architecture. Titanium adds significant array support on top of the arrays present in Java languages. In order to provide efficient mappings for the application, the parallelization architecture has to either model or benchmark library kernels to get a sense for the underlying architecture performance.