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rtl2uspec

Hsiao, Mulligan, Nikoleris and 2 others

Zenodo (CERN European Organization for Nuclear Research)18 Oct 2021Open access

NobleIDark:/48914/w1/20260515/9B154108DOI10.5281/zenodo.5492990

Abstract

The rtl2uspec tool proposed in the paper: Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations.

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