Texas Instruments (India)

This paper proposes a novel modification of the brightness preserving dynamic histogram equalization technique to improve its brightness preserving and contrast enhancement abilities while reducing its computational complexity. The modified technique, called Brightness Preserving Dynamic Fuzzy Histogram Equalization (BPDFHE), uses fuzzy statistics of digital images for their representation and processing. Representation and processing of images in the fuzzy domain enables the technique to handle the inexactness of gray level values in a better way, resulting in improved performance. Execution time is dependent on image size and nature of the histogram, however experimental results show it to be faster as compared to the techniques compared here. The performance analysis of the BPDFHE along with that for BPDHE has been given for comparative evaluation.

Radar is a key sensing technology for advanced driver assistance systems and autonomous vehicles due to its strong detection capability, long range, and robustness to environmental variations such as inclement weather and lighting extremes. As these radars demonstrate increased levels of integration and performance [1,3], it is desired to have a single multimode radar transceiver that can address the stringent form factor constraints of corner radars and the wide and narrow field-of-view requirements of front radars used in urban and highway driving, respectively. This paper presents a single-chip 76-to-81 GHz radar transceiver, which utilizes frequency-modulated continuous wave (FMCW) synthesis, 3 transmitters, and 4 receivers with integrated ADCs, built in a 45nm CMOS technology. It achieves high resolution and flexible multimode operation to address all classes of short, medium, and long range. The design also features autonomous fault monitoring of the RF chain to support system-level functional safety.

A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per TX/RX pair

A novel scheme is proposed for online condition monitoring of bond wires present in insulated gate bipolar transistor (IGBT) package. The proposed method detects bond wire degradation using on-state collector emitter voltage at the inflection point. Previously reported condition monitoring methods based on on-state collector-emitter voltage as a precursor of aging require an accurate knowledge of junction temperature which is difficult to measure online during an inverter operation. The key advantage of the proposed scheme is that it monitors the bond wire degradation irrespective of the junction temperature. Therefore, this technique is not affected by increase in junction temperature due to die attach degradation or change in ambient temperature. The proposed scheme is verified experimentally under realistic operating conditions.

PURPOSE: The purpose of this study is to investigate the feasibility of increasing the system spatial resolution and scanning speed of Hologic Selenia Dimensions digital breast tomosynthesis (DBT) scanner by replacing the rotating mammography x-ray tube with a specially designed carbon nanotube (CNT) x-ray source array, which generates all the projection images needed for tomosynthesis reconstruction by electronically activating individual x-ray sources without any mechanical motion. The stationary digital breast tomosynthesis (s-DBT) design aims to (i) increase the system spatial resolution by eliminating image blurring due to x-ray tube motion and (ii) reduce the scanning time. Low spatial resolution and long scanning time are the two main technical limitations of current DBT technology. METHODS: A CNT x-ray source array was designed and evaluated against a set of targeted system performance parameters. Simulations were performed to determine the maximum anode heat load at the desired focal spot size and to design the electron focusing optics. Field emission current from CNT cathode was measured for an extended period of time to determine the stable life time of CNT cathode for an expected clinical operation scenario. The source array was manufactured, tested, and integrated with a Selenia scanner. An electronic control unit was developed to interface the source array with the detection system and to scan and regulate x-ray beams. The performance of the s-DBT system was evaluated using physical phantoms. RESULTS: The spatially distributed CNT x-ray source array comprised 31 individually addressable x-ray sources covering a 30 angular span with 1 pitch and an isotropic focal spot size of 0.6 mm at full width at half-maximum. Stable operation at 28 kV(peak) anode voltage and 38 mA tube current was demonstrated with extended lifetime and good source-to-source consistency. For the standard imaging protocol of 15 views over 14, 100 mAs dose, and 2 × 2 detector binning, the projection resolution along the scanning direction increased from 4.0 cycles/mm [at 10% modulation-transfer-function (MTF)] in DBT to 5.1 cycles/mm in s-DBT at magnification factor of 1.08. The improvement is more pronounced for faster scanning speeds, wider angular coverage, and smaller detector pixel sizes. The scanning speed depends on the detector, the number of views, and the imaging dose. With 240 ms detector readout time, the s-DBT system scanning time is 6.3 s for a 15-view, 100 mAs scan regardless of the angular coverage. The scanning speed can be reduced to less than 4 s when detectors become faster. Initial phantom studies showed good quality reconstructed images. CONCLUSIONS: A prototype s-DBT scanner has been developed and evaluated by retrofitting the Selenia rotating gantry DBT scanner with a spatially distributed CNT x-ray source array. Preliminary results show that it improves system spatial resolution substantially by eliminating image blur due to x-ray focal spot motion. The scanner speed of s-DBT system is independent of angular coverage and can be increased with faster detector without image degration. The accelerated lifetime measurement demonstrated the long term stability of CNT x-ray source array with typical clinical operation lifetime over 3 years.

Power-aware test is increasingly becoming a major manufacturing test consideration due to the problems of increased power dissipation in various test modes as well as test implications that arise due to the usage of various lowpower design technologies in devices today. Several challenges emerge for test engineers and test tool developers, including (and not restricted to) understanding of various concerns associated with power-aware test, development of power-aware design-fortest (DFT), automatic test pattern generation (ATPG) techniques, and test power analysis flows, evaluation of their efficacy and ensuring easy/rapid deployment. This paper highlights concerns and challenges in power-aware test, surveys various practices drawn from both academia and industry, and points out critical gaps that need to be addressed in the future.

Chopping the operational transconductance amplifier (OTA) of the input integrator in a CTΔΣM is a traditional and effective way of addressing flicker noise in such modulators. Unfortunately, chopping leads to aliasing of shaped quantization noise into the signal band and degrades performance. We analyze the mechanisms of shaped-noise aliasing in OTA-RC integrators that use two-stage feedforward compensated OTAs, and show that aliasing can be largely mitigated by using an finite impulse response feedback digital-to-analog converter with its zeros placed at multiples of twice the chopping frequency. The theory is borne out by measurement results from a single-bit CTΔΣM, which achieves a peak SNDR of 98.5 dB in a 24-kHz bandwidth while consuming only 280 μW from a 1.8-V supply. Realized in a 180-nm CMOS technology, it achieves a 1/f noise corner of about 3 Hz when chopped at f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> /24.

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

Abstract. The chemical composition and volatility of organic aerosol (OA) particles were investigated during July–August 2017 and February–March 2018 in the city of Stuttgart, one of the most polluted cities in Germany. Total non-refractory particle mass was measured with a high-resolution time-of-flight aerosol mass spectrometer (HR-ToF-AMS; hereafter AMS). Aerosol particles were collected on filters and analyzed in the laboratory with a filter inlet for gases and aerosols coupled to a high-resolution time-of-flight chemical ionization mass spectrometer (FIGAERO-HR-ToF-CIMS; hereafter CIMS), yielding the molecular composition of oxygenated OA (OOA) compounds. While the average organic mass loadings are lower in the summer period (5.1±3.2 µg m−3) than in the winter period (8.4±5.6 µg m−3), we find relatively larger mass contributions of organics measured by AMS in summer (68.8±13.4 %) compared to winter (34.8±9.5 %). CIMS mass spectra show OOA compounds in summer have O : C of 0.82±0.02 and are more influenced by biogenic emissions, while OOA compounds in winter have O : C of 0.89±0.06 and are more influenced by biomass burning emissions. Volatility parametrization analysis shows that OOA in winter is less volatile with higher contributions of low-volatility organic compounds (LVOCs) and extremely low-volatility organic compounds (ELVOCs). We partially explain this by the higher contributions of compounds with shorter carbon chain lengths and a higher number of oxygen atoms, i.e., higher O : C in winter. Organic compounds desorbing from the particles deposited on the filter samples also exhibit a shift of signal to higher desorption temperatures (i.e., lower apparent volatility) in winter. This is consistent with the relatively higher O : C in winter but may also be related to higher particle viscosity due to the higher contributions of larger-molecular-weight LVOCs and ELVOCs, interactions between different species and/or particles (particle matrix), and/or thermal decomposition of larger molecules. The results suggest that whereas lower temperature in winter may lead to increased partitioning of semi-volatile organic compounds (SVOCs) into the particle phase, this does not result in a higher overall volatility of OOA in winter and that the difference in sources and/or chemistry between the seasons plays a more important role. Our study provides insights into the seasonal variation of the molecular composition and volatility of ambient OA particles and into their potential sources.

As technology scales to 32 nm and functional frequency and density continue to rise, PSN effects, which can reduce a circuit's noise immunity and could lead to failures, pose new challenges to chip manufacturers and foundries. This article provides an overview of low-power and delay testing, and surveys ongoing research for analyzing and dealing with PSN effects during delay test and timing analysis.

Several component-minimized circuit topologies for single-phase to three-phase conversion are proposed. The topologies employ fewer semiconductor devices and generate high-quality output voltages. Suitable modification to achieve active input current shaping is illustrated in detail. Analysis and simulation of the proposed schemes are carried out to show the high-performance features. Suitable guidelines for the selection of filter components and for facilitating circuit design are presented. Selected results are verified experimentally on laboratory prototype converters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Millimeterwave (mm-Wave) radar sensors operating in the 76-to-81 GHz band are a key component of advanced driver-assistance systems (ADAS) for enhanced automotive safety. The recent entry of CMOS solutions in this space has accelerated development of multi-mode Radars that can support long, medium and short-range applications [1-3]. As ADAS applications evolve to support higher levels of autonomy, there is increased demand on radar sensors for improved maximum range, velocity, and angular resolution. Emerging automotive in-cabin occupancy sensing applications are creating opportunities for short-range, high-resolution sensors operating in 60/77GHz bands (depending on the regulatory market). The unlicensed 60GHz band has also enabled industrial sensing opportunities across diverse markets such as robotics, building automation, and healthcare. Several of these broad-market applications require inexpensive and small form factor sensors that can be deployed on low cost PCBs (e.g., FR4) without expertise in mm-Wave design. In this paper, we describe our high-performance 76-to-81GHz FMCW Automotive Radar that supports multi-chip cascading to enable higher angular resolution and a compact 57-to-64 GHz single-chip Radar with integrated antennas on package. All devices are built on a 45nm bulk CMOS technology with 9 metal layers and packaged using flip-chip BGA technology.

This work presents an efficient method for motion artifact removal from ambulatory electrocardiogram (ECG) signal for heart rate variability (HRV) in wearable/portable healthcare devices. HRV is the fluctuation in the time interval between the adjacent heartbeats. Motion artifacts affect HRV analysis by creating some outliers. A two-phase method using stationary wavelet transform with level thresholding (SWT-LT) is used to remove motion artifact from the ECG signal. Multi-channel system prototype is used for ambulatory ECG signal recording which is developed using commercial integrated circuit components. Motion artifact affected ECG signals are recorded by emulating daily activity movements. Recorded ECG database (60 signals) and Motion Artifact Contaminated ECG Database (27 signals) are used for validation of the proposed SWT-LT method. Implemented results show that the proposed SWT-LT method removes various in-band motion artifacts efficiently with an average correlation coefficient of 0.9337 and an average normalized mean square error of 0.012 which are better than the other reported methods. The proposed method has shown improvement in features of HRV analysis by removing outliers due to motion artifact from the ECG signal which is verified using MATLAB app HRVTool 1.03 developed by Marcus Vollmer.

In urban areas, congested traffic results in a large number of accidents at low speeds. This paper describes an accurate and fast driver-assistance system (DAS) that detects obstacles and warns the driver in advance of possible collisions in such a congested traffic environment. A laboratory prototype of the system is built and tested by simulating different weather conditions in the laboratory. The proposed DAS is also suitable as a parking-assistance system. Ultrasonic sensors are used to detect obstacles in this paper because they have several advantages over other types of sensors in short-range object detection. Multiple sensors are needed to get a full-field view because of the limited lateral detectable range of ultrasonic sensors. Furthermore, crosstalk is a common problem when multiple ultrasonic sensors are used. A simple microcontroller-based method to reduce crosstalk between sensors is described, which is achieved by firing each transducer by a pseudorandom number of pulses so that the echo of each transducer can uniquely be identified. Existing DASs need more time to reliably detect the objects, making them unsuitable for DASs, where time is a critical factor. A method to reduce the obstacle detection time of the system is also proposed. The cost of this high-performance system is expected to be very reasonable. All the practical implementation details are included. Extensive experimentation has been carried out, and the results confirm the speed and reliability of the presented system.

Dynamic voltage (IR) drop, unlike the static voltage drop depends on the switching activity of the design, and hence it is vector dependent. In this paper we have highlighted the pitfalls in the common design closure methodology that addresses static IR drop well, but often fails to bound the impact of dynamic voltage drops robustly. Factors that can affect the accuracy of dynamic IR analysis and the related metrics for design closure are discussed. A structured approach to planning the power distribution and grid for power managed designs is then presented, with an emphasis to cover realistic application scenarios, and how it can be done early in the design cycle. Care-about and solutions to avoid and fix the Dynamic voltage drop issues are also presented. Results are from industrial designs in 45 nm process are presented related to the said topics.

A programmed pulsewidth modulation (PWM) technique for selectively eliminating several lower-order harmonics at the output of a neutral point clamped (NPC) inverter topology is investigated. The switching function approach is utilized to derive relevant analytical expressions for input/output variables. A thorough evaluation of the NPC inverter topology based on the switching function approach is described. Optimal power control strategies for an NPC inverter employing programmed PWM patterns are proposed. For a constant-frequency variable-voltage NPC inverter power supply, the proposed strategy is to maintain a minimum specified total harmonic distortion employing a low-output impedance filter. In the case of an NPC inverter powering an AC motor drive, the proposed strategy is to maintain a minimum specified harmonic current factor. The proposed power control strategies are achieved without substantial increase in inverter switching frequency and are therefore suitable for high-power applications employing gate-turn-off-thyristor (GTO) type devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, we present the power control problem in CDMA wireless data networks in the analytical setting of noncooperative game theory. User satisfaction is represented as a net utility function, which is the difference of a strictly concave function, based on signal to interference ratio, and a cost term on user's power. A detailed analysis for the existence and uniqueness of Nash equilibrium for the above noncooperative game is presented. Next, a decentralized power control algorithm is developed which converges to the Nash equilibrium, as demonstrated by both analytical and simulation methods. The framework is then extended to the multicell case, making user utilities depend on base-station assignment as well as powers. We propose a generalized algorithm that can handle base station assignment and hand-off, as well as power control, and study by extensive simulations its performance in a dynamic environment.

The linearity of conventional active-RC filters is limited by the operational transconductance amplifiers (OTAs) used in the integrators. Transconductance-capacitance (Gm-C) filters are fast and can be linear- however, they are sensitive to parasitic capacitances. We explore the Gm-assisted OTA-RC technique, which is a way of combining Gm-C and active-RC integrators in a manner that enhances the linearity and speed of the latter, while adding negligible extra noise or power dissipation. Measurements from a fifth-order Chebyshev filter with 20 MHz bandwidth, designed in a 0.18 μ m CMOS process, demonstrate the efficacy of Gm-assistance in an active-RC integrator.

The input referred offset voltage occurring in the full latch V/sub DD/ biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by /spl plusmn/2.5% variation in V/sub T/ and /spl plusmn/5% variation in /spl beta/, from typical values. Effect of various design parameters on the sense amplifier offset has been studied and reported. It has been shown that the rise time of the sense amplifier enable signal (SAEN) has a profound effect on the offset voltage. The slower transition of SAEN signal is proposed to result in high speed as well as low-power consumption in SRAM application. An analytical model has been derived for simplified latch to model the effect of rise time of SAEN signal on offset voltage.

In this paper, we present Bi-Modal Cache - a flexible stacked DRAM cache organization which simultaneously achieves several objectives: (i) improved cache hit ratio, (ii) moving the tag storage overhead to DRAM, (iii) lower cache hit latency than tags-in-SRAM, and (iv) reduction in off-chip bandwidth wastage. The Bi-Modal Cache addresses the miss rate versus off-chip bandwidth dilemma by organizing the data in a bi-modal fashion - blocks with high spatial locality a reorganized as large blocks and those with little spatial locality as small blocks. By adaptively selecting the right granularity of storage for individual blocks at run-time, the proposed DRAM cache organization is able to make judicious use of the available DRAM cache capacity as well as reduce the off chip memory bandwidth consumption. The Bi-Modal Cache improves cache hit latency despite moving the metadata to DRAM by means of a small SRAM based Way Locator. Further by leveraging the tremendous internal bandwidth and capacity that stacked DRAM organizations provide, the Bi-Modal Cache enables efficient concurrent accesses to tags and data to reduce hit time. Through detailed simulations, we demonstrate that the Bi-Modal Cache achieves overall performance improvement (in terms of Average Normalized Turnaround Time (ANTT)) of 10.8%, 13.8% and 14.0% in 4-core, 8-core and 16-coreworkloads respectively.