A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

Harwood, Mike; Warke, N.; S. Simpson, R.; Leslie, Tom; Amerasekera, A.; Batty, Sean; Colman, D.; Carr, Eugenia; Gopinathan, Venu; Hubbins, Steve; Hunt, P.C.; Joy, Andy; Khandelwal, Pulkit; Killips, Bob; Krause, Thomas; Lytollis, Shaun; J. Pickering, A.; Saxton, Mark; Sebastio, David; Swanson, Graeme; Szczepanek, Andre; Ward, Terry; Williams, Jeff; Williams, Richard; Willwerth, Tom

doi:10.1109/isscc.2007.373481

Public

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

Shared by NobleBlocks on Feb 1, 2007 • 12:00 AM UTC

Authors:

Mike Harwood

N. Warke

R. S. Simpson

Abstract

A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.o...

Subject

SerDes

Baud

Backplane

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