Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory

Fukuzumi, Y.; Katsumata, Ryota; Kito, Masaru; Kido, M.; Satô, Mitsuru; Tanaka, Hiroyasu; Nagata, Yuzo; Matsuoka, Y.; Iwata, Yoshihisa; Aochi, Hideaki; Nitayama, A.

doi:10.1109/iedm.2007.4418970

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Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory

Shared by NobleBlocks on Dec 1, 2007 • 12:00 AM UTC

Authors:

Y. Fukuzumi

Ryota Katsumata

Masaru Kito

Abstract

Optimal process integration for array devices of bit-cost scalable (BiCS) flash memory is successfully developed. We adopt SiN-based gate dielectrics for the consistency with the 'gate-first' process which is unique to BiCS flash technology, and 'macaroni' body FETs for better controllability over t...

Subject

Scalability

Flash memory

Flash (photography)

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