Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style

Reddy Ramireddy, Gangadhar; V. R. Ravindra, J.; Kamatham, Harikrishna

doi:10.1109/ems.2013.116

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Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style

Published • Nov 1, 2013

Authors:

Gangadhar Reddy Ramireddy

J. V. R. Ravindra

Harikrishna Kamatham

Abstract

In this paper a novel method has been proposed for the problem of repeating a transistor controlled by the same input in two parallel branches in Branch Based Logic- Pass Transistor Full Adder (BBL-PT FA). In BBL-PT FA carry block is designed by using branch based logic style and sum block is with p...

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Adder

Transistor

Transistor count

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