Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology

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Published in 2013 European Modelling Symposium • Nov 20, 2013

Authors:

Narasimha Rao Konijeti

J. Ravindra

Pandurangaiah Yagateela

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Highlights, strengths & weaknesses, commercial applications, and societal impact — written for this paper on demand.

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