A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Kuroda, Tadahiro; Fujita, Takeshi; Mita, S.; Nagamatsu, T.; Yoshioka, S.; Suzuki, Kojiro; Sano, Fumihiko; Norishima, M.; Murota, Masayuki; Kako, M.; Kinugawa, M.; Kakumu, M.; Sakurai, T.

doi:10.1109/jssc.1996.542322

Public

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Shared by NobleBlocks on Nov 1, 1996 • 12:00 AM UTC

Authors:

Tadahiro Kuroda

Takeshi Fujita

S. Mita

Abstract

A 4 mm/sup 2/, two-dimensional (2-D) 8/spl times/8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-/spl mu/m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipati...

Subject

Dissipation

Discrete cosine transform

CMOS

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