A 29-ns 64-Mb DRAM with hierarchical array architecture

Nakamura, M.; Takahashi, Tsuyoshi; Akiba, T.; Kitsukawa, G.; Morino, Mario; Sekiguchi, Tomonori; Asano, Isamu; Komatsuzaki, K.; Tadaki, Y.; Cho, SangLyul; Kajigaya, K.; Tachibana, T.; Sato, Koichi

doi:10.1109/4.535414

Public

A 29-ns 64-Mb DRAM with hierarchical array architecture

Shared by NobleBlocks on Jan 1, 1996 • 12:00 AM UTC

Authors:

M. Nakamura

Tsuyoshi Takahashi

T. Akiba

Abstract

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs,...

Subject

Dram

Computer science

Architecture

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