Texas Instruments (United Kingdom)

This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200 K to 800 K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST controller for at-speed testing. Comparative data on fault grades and area overhead between automatic test pattern generation (ATPG) and logic BIST are reported. The experimental results demonstrate that with automation of the proposed solutions, logic BIST can achieve test quality approaching that of ATPG with minimal area overhead and few changes to the design flow.

A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per TX/RX pair

High voltage applications such as electric motor controllers, solar panel power inverters, electric vehicle battery chargers, uninterrupted and switching mode power supplies benefit from the galvanic isolation of contactless current sensors (CCS) [1]. These include magnetic sensors that sense the magnetic field emanating from a current-carrying conductor. The offset and resolution of Hall-effect sensors is in the μT-level [1-3], in contrast to the μT-level accuracy of integrated-fluxgate (IFG) magnetometers [4]. Previously reported sampled-data closed-loop IFG readouts have limited BWs as their sampling frequencies (4) are limited to be less than or equal to the IFG excitation frequency, f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXC</inf> [5-7]. This paper describes a differential closed-loop IFG CCS with f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</inf> >f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXC</inf> . The differential architecture rejects magnetic stray fields and achieves 750x larger BW than the prior closed-loop IFG readouts [6-7] with 10×better offset than the Hall-effect sensors [1-3].

In networking systems today data rates are increasing beyond 15Gb/s and yet the installed backplanes are made of low cost materials with losses in excess of 30dB at 7.5GHz. Standards, such as IEEE802.3ap-10GBASE-KR and OIF CEI25G, are specifying SerDes requirements for channels with 25dB loss at Nyquist and this has driven the development of SerDes with 4 or 5 tap DFEs. Until now, solutions for 34dB or more channel loss have been limited to 10.3Gb/s or below, whereas this paper describes an adaptive 14-tap DFE that achieves a 1017 BER across a 34dB loss channel at 16Gb/s for a power of 235mW/lane. A baud-rate CDR technique is specifically developed that gives excellent locking characteristics and alignment for use with a speculative DFE together with an enhanced swing TX voltage mode driver.

This paper presents a novel algorithm for on-road obstacle detection based on stereo cameras. The proposed algorithm significantly reduces the complexity disparity calculations involved when using a stereo vision technique. Many recent stereo-vision based obstacle detection systems require a dense disparity map and, then, locate the obstacles according to the depth information. However, calculating the correspondence for each pixel is very time consuming. In automotive applications object detection must be performed in real-time. The proposed algorithm uses given parameters of stereo cameras to determine the disparity search range of the pixels assuming all the pixels are on the road surface. According to the predefined search range for the road surface, the true disparities of obstacles are not included. Therefore, large errors will be introduced during block matching which indicate obstacle positions. This new system only consumes less than 10% of the traditional block-based disparity calculations. The core part of the proposed algorithm was implemented on the TI DM648 platform and achieved real-time performance.

The growing performance and decreasing price of embedded processors are opening many doors, for both developers in the industry and in academia. However, the complexities of these systems can create serious developmental bottlenecks. Sophisticated software packages such as OpenCV can assist in both the functional development and educational aspects of these otherwise complex applications; such tools lend themselves very well to use by the academic community, in particular in providing examples of algorithm implementation. However the task of migrating this software to embedded platforms poses its own challenges. This paper will review how to mitigate some of these issues, including C++ implementation, memory constraints, floating-point support, and opportunities to maximise performance using vendor-optimised libraries and integrated accelerators or co-processors. Finally, we will introduce a new effort by Texas Instruments to optimise vision systems by running OpenCV on the C6000™ digital signal processor architecture. Benchmarks will show the advantage of using the DSP by comparing the performance of a DSP+ARM® system-on-chip (SoC) processor against an ARM-only device.

The TMS320C80 is a programmable, parallel processing DSP. The test approach was an engineering mix of design for testability, test view creation, and verification. This mixture facilitated timely test generation and had other important benefits. We document the overall test methodology and the benefits derived therein.

Video surveillance systems have become relatively cheap consumer products employed in the most diverse scenarios. Digital IP cameras can deliver very high quality images and can be directly connected to the Internet. As digital circuits become smaller and faster, video surveillance sensors can be equipped with general processors and DSPs. Smart video analytics algorithms can thus be embedded in the surveillance sensors, for fast at-camera processing. In this presentation an embedded smart surveillance system for object and people tracking, using an IP PTZ camera, which can pan and tilt to follow the target will be presented. The system is implemented on the DM6437 Evaluation Module based on the TMS320DM6437 processor from Texas Instruments. The PTZ camera is driven by our developed tracking algorithm via HTTP-based commands, to keep the target always in the field of view. The system runs in real-time at 25 frames per second, with a frame resolution of 360×288 pixels.

High Speed Serializer Deserializers (serdes) are traditionally tested using functional BIST. This paper presents an improved BlST for testing the digital part of a serdes using circular BET.

Lab measurement and simulation results are presented to show how passive capacitive microwave filters along flip-chip package traces can be used to overcome the capacitive discontinuity at the output port of SerDes transceivers to improve link performance. The technique is further developed to demonstrate its ability to shape the near-end eye pattern to improve its height and/or jitter at different data rates up to 17Gbps. The benefits of the technique for devices which deploy many 10's or 100's of SerDes links are highlighted.

Publication in the conference proceedings of EUSIPCO, Glasgow, Scotland, 2009

High-speed SerDes signals are significantly distorted by the time they leave the package. The distortion is caused by excess capacitive loading at points along the signal path, causing reflections. The reflections can be minimized through design modifications, added structures for compensation, filters, and characteristic impedance shifts.

Starting a digital signal processing (DSP) implementation course can be a daunting task, especially with the advanced DSP algorithms, complex DSP processor architectures and sophisticated development tools that are developed to satisfy consumer demands. These courses can be split into disciplines such as control, audio and video. In this paper the authors are addressing the concerns associated with fast-growing DSP chips and tools and the impact they have on teaching DSP implementation. The authors also provide solutions, advice and suggestions on how to select a DSP, set a DSP implementation course and the associated laboratory hardware and software that fit a specific application.

We demonstrated a scalar atomic magnetometer using a microfabricated Cs vapor cell. The atomic spin precession is driven by an amplitude-modulated circularly-polarized pump laser resonant on the D1 transition of Cs atoms and detected by an off-resonant linearly-polarized probe laser using a balanced polarimeter setup. Under a magnetic field with amplitude in the Earth's magnetic field range, the magnetometer in the gradiometer mode can reach sensitivities below 150fT/√Hz, which shows that the magnetometer by itself can achieve sub-100fT/√Hz sensitivities. In addition to its high sensitivity, the magnetometer has a bandwidth close to 1 kHz due to the broad magnetic resonance inside the small vapor cell. Our experiment suggests the feasibility of a portable low-power and high-performance magnetometer which can be operated in the Earth's magnetic field. Such a device will greatly reduce the restrictions on the operating environment and expand the range of applications for atomic magnetometers, such as detection of nuclear magnetic resonance in low magnetic fields

The challenge facing SerDes (Serialiser De-Serialiser) designers is common with all current communications technologies. Industry advances show a trend to increase speed, reduce power and improve efficiency. In this article a novel line driver that can operate at speeds of up to 40 Gbps with a power supply of 1 V and a power consumption of 4.54 mW/Gb/s is presented. Pre-distortion on the front-end is used to maintain signal integrity.

This paper describes how the RSA (rake search accelerator) on Texas Instruments TCI6482 and TCI6488 DSP's can be used instead for accelerating the transmit functions of CDMA (code division multiple access) based standards like the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> generation mobile phone standard 3GPP. The architecture of the accelerator is overviewed together with how it is connected to the DSP and how it is used in conjunction with standard DSP software to implement the chip-rate transmit functionality of a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> generation base-station. Discussion includes real time processing, latency requirements and software structuring for handling both single and multi-sector base-station on a single chip DSP from symbol rate data all the way to baseband CDMA data.