Vardhaman College of Engineering

UniversityHyderabad, India

Research output, citation impact, and the most-cited recent papers from Vardhaman College of Engineering. Aggregated across the NobleBlocks index of 300M+ scholarly works.

Total works

Citations

148

h-index

i10-index

Also known as

Vardhaman College of Engineering

Top-cited papers from Vardhaman College of Engineering

Data labeling method based on cluster purity using relative rough entropy for categorical data clustering

H. Venkateswara Reddy, S. Viswanadha Raju, P. K. Agrawal

201317doi:10.1109/icacci.2013.6637222

Clustering is an important technique in data mining. Clustering a large data set is difficult and time consuming. An approach called data labeling has been suggested for clustering large databases using sampling technique to improve efficiency of clustering. A sampled data is selected randomly for initial clustering and data points which are not sampled and unclustered are given cluster label or an outlier based on various data labeling techniques. Data labeling is an easy task in numerical domain because it is performed based on distance between a cluster and an unlabeled data point. However, in categorical domain since the distance is not defined properly between data points and between data point with cluster, then data labeling is a difficult task for categorical data. In this paper, we have proposed a method for data labeling using Relative Rough Entropy for clustering categorical data. The concept of entropy, introduced by Shannon with particular reference to information theory is a powerful mechanism for the measurement of uncertainty information. In this method, data labeling is performed by integrating entropy with rough sets. In this paper, the cluster purity is also used for outlier detection. The experimental results show that the efficiency and clustering quality of this algorithm are better than the previous algorithms.

Dielectric, Ferroelectric and Piezoelectric Properties of Sr0.8Na0.1Nd0.1Bi4Ti4O15Prepared by Sol Gel and Solid State Technique

Rizwana, P. Sarah

2014· Ferroelectrics12doi:10.1080/00150193.2014.932616

Effect of lower ionic radii (Na and Nd) substitution in A-site on the structure, dielectric, ferroelectric and piezoelectric properties of SrBi4Ti4O15 (SBT) is investigated in this paper. The samples are prepared by solid state double sintering method and sol gel method based on pechini process. Substitution of smaller ions reduced the dielectric constant and remanent polarization values. But sol gel samples showed good dielectric and ferroelectric properties. A-site substitution has resulted in improved Curie temperature and piezoelectric properties. As a result, Na and Nd modified SBT ceramics are found to be excellent high temperature piezoelectric materials.

Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology

Narasimha Rao Konijeti, J. V. R. Ravindra, Pandurangaiah Yagateela

20138doi:10.1109/ems.2013.117

Low-power circuits are becoming more attractive due to growing of portable device markets. The 1-bit full adder cell is the key building block for any ASIC design. Designing of such low power full-adder circuits is always a challenging concern for any design research. In this paper, we present a new full-adder cell which is designed with multiple pass transistor logic styles, in which some of them use no power/ground rail approach that helps to reduce power. The proposed full-adder was compared with existing low power full adder cells. All these full-adder cells are designed using Generic Process Design Kit (GPDK) 45 nm technology and they are designed in Cadence virtuoso environment and simulated with Cadence spectre simulator. Pre-layout test bench Simulation results shown that proposed full-adder has the advantage of 60% power savings, 32% Speed Improvements and 72% energy improvements.

Study of Effect of Doping on Grain and Grain Boundary Parameters of Sr1−2xNaxNdxBi4Ti4O15(x = 0−0.5) Ceramics Using Impedance Spectroscopy

Rizwana, P. Sarah

2014· Ferroelectrics6doi:10.1080/00150193.2014.932611

AbstractDetailed impedance studies are done on Sr1−2xNaxNdxBi4Ti4O15 (x = 0, 0.1, 0.2, 0.4 and 0.5) system prepared by both sol gel and solid state method. An effort is made to explain the different mechanisms involved in the conduction mechanism through impedance studies. Grain boundary conduction dominates over the grain conduction. Capacitance is associated with the net polarization of ferroelectric domains. Grain boundaries required higher activation energies for hopping than the grains.Keywords: Impedance spectroscopygraingrain boundaryresistancecapacitancerelaxation frequency

A novel power-aware and high performance full adder cell for ultra-low power designs

Gangadhar Reddy Ramireddy, J V R Rovinara

20143doi:10.1109/iccpct.2014.7055037

The design of low power VLSI circuit is a challenging task at deep sub-micron technologies. Full adder is a basic key element of many arithmetic circuits like multiplexers, subtracters, dividers, etc. Since the technology is changing at a rapid pace, it is essential to develop and design new methodologies or circuits, which are going to reduce power consumption and worst case delay of circuits. In this regards, this paper is proposing a new circuit design for obtaining full adder functionality of 1-Bit. The proposed full adder is designed with 10-Transistors. The proposed 10-Transistor full adder uses two Low Power XOR gates and a two transistor multiplexer. All the designed circuits in this paper are captured and simulated using Virtuso Schematic Editor and Spectre simulator. These tools are part of Cadence Virtuoso Design Environment provided by Cadence Design Systems. Generic Process Design Kit(GPDK) 45nm technology file is used to get the transistor models. Prelayout simulation results turn out that the proposed 10-Transistor full adder performance better.

Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style

Gangadhar Reddy Ramireddy, J. V. R. Ravindra, Harikrishna Kamatham

20133doi:10.1109/ems.2013.116

In this paper a novel method has been proposed for the problem of repeating a transistor controlled by the same input in two parallel branches in Branch Based Logic- Pass Transistor Full Adder (BBL-PT FA). In BBL-PT FA carry block is designed by using branch based logic style and sum block is with pass transistor logic style. The modifications are done for carry block. Common transistor in parallel branches is taken out and kept one transistor for parallel branches. This method provides advantages of reduced number of transistors, decrease in die area of the design, and power dissipation. Designed circuits are simulated using spectre simulator in virtuoso tool provided by Cadence Design Systems Electronic Design Automation (EDA) tool. Simulations have been done using Generic Process Design Kits 180, 90, and 45 nanometer technology files with supply voltage of 1.8V, 1.2V, 1.1V respectively and operating frequency 500MHz. Simulation results show that the proposed solution gives better results.

Clustering Categorical Data Using Rough Membership Function

B. Suresh Kumar, H. Venkateswara Reddy, T. Ankamma Raju, Preethi Vennam

20141doi:10.1109/cicn.2014.135

Data mining automates the process of finding predictive records in large databases. Clustering is a very popular technique in data mining and is a significant methodology that is performed based on the principle of similarity. The segregation of a large database is a challenging and time consuming task. For this purpose, an approach called data labeling through sampling technique is used. Using this approach segregating large databases not only gets easier but also it increases the efficiency of clustering technique. Initially a sample data is retrieved from a large database for clustering and the residual unsampled data points are compared with the clustered data from which the similar data points are clustered and the dissimilar one are considered as outliers based on various data labeling techniques. These data labeling techniques are easier to apply in the numerical domains, whereas in the categorical domains this is a complicated task as the distance among data points are incalculable. Further the proposed methodology gives a data labeling technique based on the changes in the similarities after including unlabeled data point into existing cluster for categorical data using cluster entropy in rough set theory. The experimental results show that the proposed algorithm is an efficient and high quality clustering algorithm compared to that of the previous ones.

Frequency and Temperature Dependence of Electrical Properties of Zirconium and Neodymium Substituted SrBi4Ti4O15Ceramics

B. Mamatha, M. Buchi Suresh, P. Sarah

2013· Ferroelectrics1doi:10.1080/00150193.2013.814017

Polycrystalline ceramics SrNdxBi4-xZryTi4-yO15 (x = 0.00, 0.025, 0.05, 0.075, 0.1, y = 0.00, 0.025) were prepared by using the conventional solid-state reaction method. Orthorhombic structure with single phase was identified by X-ray diffractogram (XRD). Impedance, AC and DC conductivity studies were investigated in the frequency range, 1 Hz–1 MHz and temperature range from room temperature (RT) to 600°C. From impedance data, various parameters grain (bulk) resistance (Rg) and capacitance (Cg), grain boundary resistance (Rgb) and capacitance (Cgb) were determined. Grain and grain boundary relaxation times (τg, τgb), activation energies for relaxation and conduction were evaluated as a function of temperature.

A novel polynomial basis multiplier for arbitrary elliptic curves over GF (2m)

Abdul Mosin, J. V. R. Ravindra

2014doi:10.1109/i2ct.2014.7092022

Finite field GF (2 m ) arithmetic plays a crucial role in applications like Computer algebra, Coding theory and Elliptic Curve Cryptography (ECC). The GF (2 m ) multiplication is considered significant building block among the finite field arithmetic operations. A new shift and add polynomial basis multiplier over GF (2 m ) is explained in this paper for irreducible GF (2 m ) generating polynomials f (x) = x m +x(k t ) + x(k t-1 ) + ...... x(k 1 ) + 1. The multiplier which is proposed has less area and minimum number of gates. In this paper the RTL code is compiled and synthesized using Encounter RTL Compiler tool provided by the Cadence Design Systems. Synthesis is carried out using the TSMC 135nm, 65nm and 40nm technology files.

A novel modulo 2n &#x002B; 1 fused multiply-adder unit for secured VLSI architectures

N. Sainath Reddy, J. V. R. Ravindra

2014doi:10.1109/iccpct.2014.7055038

There is increase in computer performance exponentially in past few decades which led to demand in low power and high speed arithmetic circuits which is highly challenging in designing of such kind of circuits. The Fused Multiply Add (FMA) is one of the most efficient designs from the arithmetic designs. This paper presents a novel FMA which is implemented by using modulo 2 n + 1 adder and multiplier to achieve low power and high speed. The synthesis is carried out in RTL Complier using TSMC 130nm, 90nm, 65nm and 40nm technology files. In order to show the confidence of the proposed FMA it has been compared with existing one FMA. The results show that the proposed FMA has better performance in terms of delay, power and area.

A Roughset Based Data Labeling Method for Clustering Categorical Data

H. Venkateswara Reddy, S. Viswanadha Raju

2014· International Conference on Engineering of Complex Computer Systemsdoi:10.1109/iceccs.2014.86

Data mining presets the process of finding analytical accounts in huge databases. Clustering is a one of efficient technique in data mining and it is performed based on the principle of similarity. Clustering the large database is a demanding and time consuming task. For this reason, an approach called data labeling through sampling technique is used. Data labeling is process of clustering the un sampled data objects into appropriate clusters. In this approach clustering the data is easy and also it improves the efficiency of clustering. In this method initially a sample dataset is chosen from a large database for clustering when initial clustering is completed, and the unsampled data objects are compared with the presented clusters. As a result, the similar data objects are given proper clustered labels and the dissimilar ones are treated as outliers. These data labeling methods are easier to execute on the numerical data, but it is complicated task for the categorical data because the distance among data objects does not exist. In the proposed method, a new and efficient data labeling technique is used to cluster the categorical data based on the cluster entropy in rough set theory. It is shown through the experimental results that the proposed algorithm is efficient and produces high quality clusters than previous clustering methods.

Polarization Reconfigurable Antenna: Design and Analysis

Praveen Kumar Kancherla, K. Satish Reddy, Harswaroop Vaish

2015

This paper presents an analysis and design of a polarization reconfigurable microstrip patch antenna fed with single and dual feeds operating at WLAN frequency. For a single feed structure a square patch is designed first and is perturbed for obtaining circular polarization. Using PIN diodes this design can be made to generate different polarizations. In case of a dual feed structure the radiating square patch has dual feeding provision and when these dual feeds are excited simultaneously with a phase difference of 90°, a circularly polarized wave is obtained. Depending on the relative phase difference between the feeds different polarizations are obtained. The antenna is designed for Taconic (er=2.65) substrate and the simulated results of both the antenna designs are compared and analyzed. Good circular polarization is achieved with dual feed with axial ratio bandwidth of 33.85% when compared with that of the single feed antenna design. Keywords: Patch antenna, polarization, auxiliary ratio

Dielectric and ferroelectric properties of lanthanum doped SrBi<inf>4</inf>Ti<inf>4</inf>O<inf>15</inf> ferroelectric ceramics

K. Ashok, V.S. Raju, S. Chandralingam, P. Sarah

2011doi:10.1109/ivec.2011.5747039

Bismuth layer structure ferroelectrics (BLSFs) have attracted intensive investigation for the potential use in non volatile ferroelectric random access memory (FeRAM) and piezoelectric devices suitable at high temperature. Bismuth layere structured compounds with general formula of (Bi 2 O 2 ) 2+ (A m-1 B m O 3m+1 ) 2- are firstly found by Aurivillius 1-3 . The structure of these compounds can be described as pseudo-pervoskite (A m-1 B m O 3m+1 ) 2- slabs separated by (Bi 2 O 2 ) 2+ layeres along the crystallographic c-axis 4 . The 12-coordinated A site can be occupied by such cations as La 3+ , Bi 3+ , Ba 2+ , Sr 2+ , Pb 2+ , Ca 2+ , Na + , etc. While the octahedral-coordinated B site can be occupied by W 6+ , Nb 5+ , Ta 5+ , Ti 4+ , etc. Lanthanum substituted BiT (Bi 4 Ti 4 O 12 ) known as BLT has been extensively investigated. With this substitution, BLT shows relatively large P r , low synthesis temperature and good fatigue endurance which makes it a potential candidate for FeRAM application. So, lanthanum doping is an effective way to improve the ferroelectric and fatigue properties of Bi 4 Ti 4 O 12 . Lanthanum doped Bismuth layer structure ferroelectrics (BLSFs) ceramics SrBi 4-x La x Ti 4 O 15 (x=0, 0.025, 0.050, 0.075, 0.1) were prepared by solid state reaction method. X-Ray diffraction pattern showed that single phase was formed when x=0- 0.1. Morphological studies were carried out by SEM analysis. It was found that crystal lattice constant, dielectric and electrical properties of SBT ferroelectrics varied appreciably with amount of doping. Dielectric measurements in the frequency range 100Hz-1MHz were made using an impedance analyzer (Wayne Kerr 6500P) and the measurements were carried out from RT to 600°C. The ferroelectric hysteresis loop was traced at room temperature by a standard P-E loop tracer based on sawyer-tower circuit.

Search all NobleBlocks papers mentioning “Vardhaman College of Engineering” →