Texas Instruments (Japan)

The electronic packaging industry has been using electroless Ni(P)∕immersion Au as bonding pads for solder joints. Because of the persistence of the black pad defect, which is due to cracks in the pad surface, the industry is looking for a replacement of the Ni(P) plating. Several Cu-based candidates have been suggested, but most of them will lead to the direct contact of solder with Cu in soldering. The fast reaction of solder with Cu, especially during solid state aging, may be a concern for the solder joint reliability if the package will be used in a high temperature environment and is highly stressed. In this work, the reaction of eutectic SnPb solder with electrodeposited laminate Cu is studied. Emphasis is given to the evolution of the microstructure in the interfacial region during solid state aging and its effect on solder joint reliability. A large number of Kirkendall voids were observed at the interface between Cu3Sn and Cu. The void formation resulted in weak bonding between solder and Cu and led to brittle fracture at the interface in the ball shear and pull tests. The experimental results indicate that a barrier for Cu diffusion may be needed between the solder and the type of Cu used in the test vehicle for the packages that will experience high temperature (>100°C) and high stress.

The drive for Pb-free solders in the microelectronics industry presents several new reliability challenges. Examples include package compatibility with higher process temperatures, new solder compound failure mechanisms, and the selection of the proper Pb-free alloy to maximize product lifetime. In addition to the challenges posed by the Pb-free material conversion, the migration of market focus from desktop computing to portable applications is changing the critical system failure mode of interest from conventional temperature cycling (T/C) induced solder fatigue opens to drop impact induced solder joint fracture. In this paper a study was conducted to investigate the influence of intermetallic compound (IMC) growth on the solder joint reliability of Pb-free ball grid array (BGA) packages under drop loading conditions. Thermal aging at homologous temperatures between 0.76 and 0.91 with microstructural analysis was conducted to analyze the solid phase IMC growth at the solder to BGA pad interface. Component level,ball shear and pull tests were also conducted to investigate the aging effect on solder joint strength. A key finding from this work is that Kirkendall voids formed at the bulk solder to package bare Cu pad interface under relative low 100/spl deg/C aging. Void formation and coalesce is shown to be the dominant mechanism for solder joint strength and board level drop reliability degradation.

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.

The wide DR CMOS image sensor incorporates a lateral overflow capacitor in each pixel to integrate the overflow charges from the photodiode when it saturates. The 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel, 1/3" VGA sensor fabricated in a 0.35 /spl mu/m 3M2P CMOS process achieves a 100 dB dynamic range with no image lag, 0.15 mV/sub rms/ random noise and 0.15 mV fixed pattern noise.

Interface traps are shown to significantly affect the gate-induced drain-leakage current in a MOSFET or gated diode. The leakage current in a p/sup +/-gated diode can increase by two orders of magnitude when the interface trap density is increased from 10/sup 11/ to 10/sup 12/ cm/sup -2/-eV/sup -1/. The fact that thermal annealing at 300 degrees C can eliminate both the generated interface traps and the excessive leakage current supports the close correlation between the two. The p/sup +/-gated diode is found to be more susceptible to this interface-trap related leakage current than the n/sup +/-device, which can be explained qualitatively by an interface-trap-assisted tunneling model.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper describes recent progress in technology of low light level image sensing using CCD sensors that multiply charge by impact ionization before its conversion into a voltage. The paper presents a brief description of the concept, the outline of a typical sensor design with some important details related to prevention of serial register blooming and achieving high dynamic range (DR), and then focuses primarily on the measurement and analysis of noise components that are important in these devices. The paper describes the theory of excess noise, shows the computation of the output signal probability distribution function (PDF), and the derivation of formula for the excess noise factor (ENF). Finally, it is concluded that under suitable conditions it is possible to achieve a single photon (electron) detection (SPD) performance.

We have found excellent electrical characteristics in germanium oxide grown by plasma oxidation for germanium metal-insulator-semiconductor gate dielectric applications. An oxygen plasma stream generated by electron cyclotron resonance was used to oxidize a germanium surface without substrate heating. A transmission electron microscope observation revealed that the obtained germanium oxide/germanium interface is atomically smooth. The energy distribution of interface trap density ( D it ) in the upper half of the p-type germanium band gap was measured by the ac conductance method. It is shown that the D it at the midgap is ∼6 ×10 10 cm -2 ·eV -1 and increases exponentially as the energy increases to the conduction-band edge.

In order to identify the origin of dielectric relaxation of Pt/Ba1-xSrxTiO3/Pt thin-film capacitors, effects of post-annealing in oxygen ambient on their electrical properties were investigated. From comparison of the electrical properties of as-deposited and post-annealed capacitors, it is concluded that electrons from oxygen vacancies in the interfacial depletion region are the origin of the phenomenon.

A precise on-chip voltage generator for gigascale DRAM's with a negative word-line scheme is described. It combines a charge-pump regulator and a series-pass regulator, and it also includes a positive and negative offset voltage generator that uses a bandgap generator with a differential amplifier. The proposed circuit was experimentally evaluated with a test device fabricated using a 0.3-/spl mu/m process. The simulation results show that the series-pass regulator suppresses the noise on a word-line low voltage (negative) to below 30 mV for the word-line transient and V/sub BB/ bouncing. A dc-voltage error of less than 6% without trimming is confirmed for the positive and negative offset voltage generator through the test device. These results show that the described scheme can be used in future low-voltage gigascale DRAM's.

To investigate the mechanism of C4F8 dissociation in parallel-plate-type plasma, we used several of the latest diagnostic tools and made extensive measurements of electrons, radicals, and ions under conditions that greatly suppressed the effects of plasma-surface interaction. These measurements showed that the amount of light fluorocarbon radicals and ions increased with increasing electron density. The dissociation of C4F8 was analyzed by using rate equations, after confirming the stability and uniformity of the plasma. The total dissociation rate coefficient of C4F8 was 1×10−8 cm3/s, and CF2 radicals were mainly generated from products of C4F8 dissociation. F was mainly generated from CF2 by electron-impact dissociation and lost by pumping. We could estimate that the C2F4 density was roughly comparable to the densities of CF and CF3, and that the surface loss probability of C2F4 increased with increasing electron density. C2F4 might play an important role in the etching because of its rich polymerization characteristics.

Switching endurance properties of lead-zirconate-titanate thin-film capacitors with gold, platinum and iridium top electrodes were investigated using a pulse switching characterization technique. Lead-zirconate-titanate capacitor structure formed with Ir top and bottom electrodes exhibited superior switching endurance to Au/PZT/Ir and Pt/PZT/Ir capacitors. The difference between switched and nonswitched polarizations of an Ir/PZT/Ir capacitor reversed by bipolar pulses was more than 38 µ C/ cm 2 after 2×10 9 switching cycles. Nonswitched polarization of this capacitor for negative read-pulses decreased gradually with increase in the number of switching cycles. When positive and negative unipolar pulses, and DC biases were applied to the top electrodes of Pt/PZT/Ir and Ir/PZT/Ir capacitors, remanent polarizations of each capacitor were not changed significantly. However, nonswitched polarizations for negative read-pulses decreased with increase in the number of negative unipolar pulses applied or DC bias application time. Drastic decrease in remanent polarization of a Pt/PZT/Ir capacitor was caused only by bipolar pulse application. The reduction of nonswitched polarization for negative read-pulses suggested the formation of depletion-layer capacitances at the interfaces between top electrodes and PZT layers.

A device architecture for building high-performance and high-resolution image sensors suitable for consumer TV camera applications is introduced. The sensor elements are junction field-effect transistors that are organized in an array with their gates floating and capacitively coupled to common horizontal address line. The photogenerated signal is sampled one line at a time, processed to remove the element-to-element nonuniformities, and stored in a buffer for subsequent readout. The concept, which includes an intrinsic exposure control, is demonstrated on a test image sensor that has an 8-mm sensing area diagonal and 580 (H)*488 (V) pixels. The key performance parameters, in addition to a high packing density of sensing elements with a unique hexagonal shape, include high signal uniformity, low dark current, good light sensitivity, high blooming overload protection, and no image smear. The discussion covers the design and operation of the basic image-sensing element, the architecture of the array, and the operation of the on-chip circuits needed for addressing and processing of generated signals. The overall device performance is demonstrated by typical device characterization results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Interface states in almost the entire SiC band gap are observable by means of x-ray photoelectron spectroscopy (XPS) measurements under bias, although SiC is a wide-gap semiconductor having 2.9 eV band-gap energy. When a ${\mathrm{SiO}}_{2}$ layer is formed by wet oxidation at 1000 \ifmmode^\circ\else\textdegree\fi{}C on $6H\ensuremath{-}\mathrm{SiC}(0001)$ Si-faced surfaces, only a broad interface state peak is observed at \ensuremath{\sim}2 eV above the SiC valence-band maximum (VBM), while for dry oxidation at the same temperature, an additional sharp interface state peak is caused at 1.8 eV above the VBM. When the wet-oxidation temperature is increased to 1150 \ifmmode^\circ\else\textdegree\fi{}C, this 1.8-eV interface-state peak also appears. The concentration of graphitic carbon at the ${\mathrm{SiO}}_{2}/\mathrm{SiC}$ interface is found to increase with the heat treatment temperature. The 1.8-eV interface-state peak is tentatively attributed to graphitic carbon with a special structure near the interface. On the other hand, the broad 2-eV interface-state peak is attributed to Si dangling bonds at the interface. Without the 1.8-eV interface-state peak, current-voltage $(I\ensuremath{-}V)$ curves measured under x-ray irradiation deviate only slightly from the ideal $I\ensuremath{-}V$ curve (\ensuremath{\sim}0.4 V), while with this peak, the deviation becomes much larger (\ensuremath{\sim}0.8 V). XPS measurements under bias show that the $I\ensuremath{-}V$ curves under x-ray irradiation are determined by the magnitude of band bending in SiC. Therefore, the deviation from the ideal $I\ensuremath{-}V$ curve is attributed to the accumulation of holes (i.e., minority carriers), generated by x-ray irradiation, at interface states with energies between the SiC and metal Fermi levels, causing a downward SiC band-edge shift and thus resulting in a decrease in the magnitude of band bending in SiC. This result demonstrates that the interface states affect $I\ensuremath{-}V$ characteristics by a static effect (i.e., interface state charges), not by a dynamical effect (i.e., electron-hole recombination at the interface states).

In an effort to extend battery life, the manufacturers of portable consumer electronics are continually driving down the supply voltages of their systems. For example, next-generation cellular phones are expected to utilize a 1-V power supply for their digital component. To address this market, an energy-efficient, programmable digital signal processing (DSP) chip that operates from a 1-V supply has been designed, fabricated, and tested. The DSP features an instruction set and micro-architecture that are specifically targeted at wireless communication applications and that have been carefully optimized to minimize power consumption without sacrificing performance. The design utilizes a 0.35-/spl mu/m dual-V/sub t/ technology with 0.25-/spl mu/m minimum gate lengths that enables good performance at 1 V. Specifically, the chip dissipates 17 mW at 1 V, achieving 63-MHz operation with a power-performance metric of 0.21 mW/MHz.

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-/spl mu/m CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71/spl times/1.20 /spl mu/m/sup 2/, and the chip size is 15.91/spl times/9.06 mm/sup 2/. A typical access time under 3.3 V power supply voltage is 29 ns.

An optimum design theory to clarify a possible limit of achieving both high conversion gain (CG) and full well capacity (FWC) at the same time in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) in a pixel is discussed. The possible limit of both high CG and high FWC is theoretically derived from a signal-to-noise-ratio (SNR) formula at a switching point from a low light signal (S1) to a bright one (S2). Based on this theory, a 1/4-in VGA-format 5.6-mum-pixel-pitch CMOS image sensor has been fabricated through a 0.18-mum 2P3M CMOS technology. A high-quality wide-dynamic-range image sensing has been demonstrated with no significant visible noise, achieving over 32 dB of SNR for an 18% gray card.

This paper proposes the new LLC converter with unique control method. Generally, LLC resonant converter, which is controlled by PFM, has the drawback of (1) difficulty of PWM controllability, (2) difficulty of constant current limitation, and (3) narrow input voltage range limitation. These difficulties come from the resonant operation. In order to overcome those drawbacks, a hybrid control of PFM and PWM is employed for LLC. The resonant frequency is set to lower frequency to generate triangle current waveform, and the output voltage can be controlled by PWM and PFM through adjustment of resonant inductor energy. The experimental results for 48Vin, 16Vo, 80W board achieves 90% efficiency and validated this method is useful practically.

A dual-period self-refresh (DPS-refresh) scheme for low-power DRAM's is proposed. Word lines are classified into two groups according to retention test data which are stored in a PROM mode register implemented in the chip periphery. The word lines are controlled individually by combining the memory-mat-select signal and the classification signal from the PROM register. The effective refresh period can be extended by four to six times compared to the conventional self-refresh period. Data-retention current of a 64-Mb DRAM test chip featuring the proposed DPS-refresh scheme is reduced to half the conventional self-refresh current without considerable area penalty.

A new bond failure mechanism related to the new, mechanically weak, low-k dielectrics in intermetal dielectric stacks is presented. Mechanical reinforcement of the dielectric stack through the use of metal grids is demonstrated to be effective to prevent this damage. Possible failure mechanisms are discussed.

A high-sensitivity CMOS image sensor keeping a high full-well capacity has been developed by introducing a new pixel having a small floating diffusion (FD) capacitance connected to a lateral overflow integration capacitor (LOFIC) through a MOS switch. The conceptual advantage of the small FD approach over conventional column amplifier approaches is compared and demonstrated. To ensure both the high sensitivity and the high full-well capacity, the low-light and the bright-light signals (S1 and S2) are output and reproduced without a visible SNR degradation at the S1/S2 switching point. As the most critical problem, the increase of the conversion gain variation in this approach is suppressed by applying a self-aligned offset structure to the small FD. A 1/4-in VGA format CMOS image sensor fabricated through 0.18-mum 2P3M process achieves 2.2-e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms noise floor with 200-muV/e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> conversion gain and 100-ke <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> full-well capacity.